Fault-detecting monitor for integrated circuit units

ABSTRACT

A substrate supporting an operational integrated circuit and further supporting a fault-detecting monitor integrated circuit, wherein the monitor circuit samples a plurality of check points in the operational circuit to sense faulty functioning of the operational circuit, enters into a storage member an indicium of the fault status of the operational circuit, and delivers at output terminals of the substrate signals representing the indicium stored in the storage member.

United States Patent FAULT-DETECTING MONITOR FOR INTEGRATED CIRCUITUNITS- 5 Claims, 14 Drawing Figs.

US. Cl 324/158, Y 324/51, 324/73 Int. Cl GOlr 3 l 2Z GO If 3 H30. Fieldof Search 324/51, 158, 73

[56] References Cited UNITED STATES PATENTS 3,286,175 11/1966 Gel-bier324/73 3,466,544 9/1969 Balderston 324/158 Primary Examiner-Rudolph V.Rolinec Assistant Examiner'Ernest F. Karlsen Attorneys-George V.Eltgroth and Joseph B. Forman ABSTRACT: A substrate supporting anoperational integrated circuit and further supporting a fault-detectingmonitor integrated circuit, whereinthe monitor circuit samples aplurality of check points in the operational circuit to sense faultyfunctioning of the operational circuit, enters into a storage member anindicium of the fault status of the operational circuit, and delivers atoutput terminals of the substrate signals representing the indiciumstored in the storage member.

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ATENTEB JUN29 1911 FAULT-DETECTING MONITOR FOR INTEGRATED CIRCUIT UNITSThe present invention relates to an improvement of in.- tegratedcircuits, and consists of providing such circuits with means for faultdetection.

Integrated circuit units, which comprise relatively complex circuits,formed by conductive, semiconductive and insulating elements ofextremely reduced dimensions, obtained through diffusion, or deposition,or other known processes, of suitable materials on a single chip ofsemiconductive material, for instance doped silicium, according topredetermined pattern are known.

In such integrated circuit units, the chip which supports the integratedcircuits is enclosed in a suitable casing provided with a number of pinsfor connection to external circuits. The connections between such pinsand the input and output terminals of the integrated circuit are formedby very thin metallic wires soldered to the pins and to proper pads ofthe integrated circuit. Complex electronic apparatus for processing,calculating, or transmitting data comprise a great number of suchintegrated circuit units, it is thus necessary to be able to check thecorrect operation of these integrated units and, in case a fault isdetected, to identify the defective unit as soon as possible. In thepresent state of the art, this is accomplished by the use of diagnosticprograms, which provide for applying a suitable sequence of data to theinputs of the apparatus, and by checking the sequence of output dataThis requires considerable time and energy, and does not guaranteecomplete accuracy that at any period of time and during any dataprocessing operation, the computer is free from failure.

Element or circuit redundancy is also used to increase operationreliability. The number of machine failures is certainly reduced by suchmeans, but this method is very expensive and usually does not providedetection of faults nor identification of their location.

An object of the present invention is to provide means for immediatelyidentifying the integrated circuit unit involved in any detectedfailure, orat least, a restricted set of units including the defectiveunit.

An alternative object of the invention is to provide means for checking,at any time, by a simple sequence of operations, the existence ofdefective integrated units, and for positively identifying the defectiveunit, or at least a restricted set of units including the defective one.

SUMMARY OF THE INVENTION These objects are attained, according to theinvention, by providing each integrated circuit unit, comprising atleast one main circuit fabricated on a single chip, with an auxiliaryfault detecting circuit, fabricated on the same chip by processescompatible and to some extent partially common with those used forfabricating the main circuit, the auxiliary circuit comprising a logicunit, means for comparing the output of the logic unit with the outputof the main circuit, means for memorizing the result of this comparison,and means for signalling to the exterior of the integrated circuit unitthe occurrence of a fault. In addition, the auxiliary unit may consistof at least one double threshold circuit for checking that voltage inputvalues are sufficiently near to the correct input values. The auxiliarycircuit operates at a speed substantially lower than the main circuitoperating speed, so that apparent faults due to transient conditionswill not be signalled.

In addition, according to the invention, faults in an integrated circuitunit, which cannot be detected by the faultdetecting auxiliary circuitpertaining to the same integrated unit, may be detected by thefault-detecting circuit pertaining to integrated units logicallyfollowing the defective integrated unit.

The fault-detecting circuits are preferably obtained through the use ofthe Metal-Oxide-Semiconductor technique, as the components thus obtainedhave high input impedance,

reduced energy, relatively low speed of operation, high reliability, andare therefore particularly suitable for the purpose.

These and other features and advantages of the invention will beapparent from the detailed description of a preferred embodiment, whenread in conjunction with the attached drawings, in which:

FIGS. 1 to 5 show the symbols used to represent different logicfunctions. 1

FIGS. 6 and 7 show the logic networks used for obtaining two logicfunctions.

FIG. 8 shows the symbol used for a flip-flop.

FIG. 9 shows the symbol used for a "double threshold circuit.

FIG. Ml shows the logic diagram of an integrated unit comprising apartial fault-detecting circuit.

FIG. it shows the logic diagram of an integrated. unit comprising acomplete fault-detecting circuit.

FIG. 12 is a block diagram showing a plurality of interconnectedintegrated units.

FIG. I3 comprises a simplified wiring diagram of a main circuit, and'thelogic diagram of a partial fault-detecting circuit.

FIG. M comprises the wiring diagram of the same circuit as FIG. 13 andthe logic diagram-of a complete fault-detecting circuit.

The description of the different devices and circuits embodying theinvention is based on the followingassumptions.

Each integrated circuit unit comprises a chip of semiconductor materialsupportinga main circuit, or a plurality of main circuits, obtained byknown methods, and having the purpose of transferring and processing theinput signals according to specified power and speed characteristics,and an auxiliary circuit, or a plurality of auxiliary circuits, for thedetection of faults. In the drawings, thick lines are used for the maincircuits, thin lines for the auxiliary circuits. In the example shown,it is assumed that the main circuit pertains to the integrated circuitfamily known as Diode-Transistor Logic or DTL. It is obvious that thedescriptions and conclusions are valid, in principle, and ifconveniently modified, also apply to integrated circuits pertaining toother families, such as these known as Resistor Transistor Logic (RTL),Transistor- Transistor Logic (TIL), and others.

The following assumptions are made with reference to the signals to beprocessed:

a positive voltage level V, represents the logic value ONE a lowervoltage V in particular V 0 Volt represents the logic value ZERO Acircuit performing the logic function AND is represented by the symbolshown in FIG. 1.

A- circuit performing the logic function OR is represented by the symbolshown in FIG. 2.

A circuit performing the logic function NOT, or Inversion, isrepresented by the symbol shown in FIG. 3.

A circuit performing the logic function Exclusive OR, which in thisdescription will be called Diversity," is represented by the symbolshown in FIG. 4. Such circuit produces at its output a logic value ONEif, and only if, the signals at the inputs have different values, thatis one is ONE and the other is ZERO. It is well known that such circuitmay be obtained by combining the elementary circuits AND, OR, NOT, forexample, as shown in FIG. 6.

A circuit performing the Identity function is represented by the symbolin FIG. 5. It produces at its output a logic value ONE if, and only if,both inputs have the same value, that is, if they are both ONE or bothZERO. It may be obtained by combining the elementary circuits AND, OR,NOT as shown, for example, in FIG. 7.

A memory device, capable of assuming and maintaining either one of twostable positions, like the bistable circuit commonly called Flip-Flop,is represented by the symbol shown in FIG. 8. It has a setting input ESand a resetting" input ER, a direct output U1) and a negated output UN.If a signal of level ONE is applied to the input ES for a sufficienttime, while input ER is maintained at ZERO level, the flip-flop will beset in the UP position, whereby its UD output is at ONE value, and theoutput UN is at ZERO value. it remains in this condition if both inputsare at ZERO level. lfa signal ONE of sufficient duration is applied tothe ER input, while the ES input remains at ZERO level, the flip-flopgoes into the DOWN condition, whereby the output UD is ZERO and theoutput UN is ONE. Contemporary application of level ONE signals to bothinputs is not permitted.

A double threshold circuit, having a definite number of inputs ET and anoutput UT is represented by the symbol shown in FIG. 9. It produces atits output a value ZERO if, and only if, all inputs ET are maintainedeither at a voltage between the value V and a first threshold value VShigher than V or to a voltage between a second threshold value, V8higher than V8,, and lower than V,, and a value at least equal to V Theoutput logic level will be ONE if, and only if, at least one input is ata voltage between the threshold values V8,, and V8,. If, as it has beenassumed, V =O V, and V,=5V, the threshold values, for example, may be VS=l V, VS,=3.5 V.

FIG. is a block diagram representing, in a general way, a deviceaccording to the invention. An integrated circuit unit is fabricated ona silicon chip 2, and comprises a main circuit 3 having three inputs 4,5, 6 and anoutput 7.

The circuit 3 is fed by an appropriate source of voltage throughconductor 8 and is connected to ground through conductor 9. The entireintegrated unit is enclosed in an airtight casing represented by thebroken line 1, and the connecting pins are represented by the smallcircles on this line.

Three main circuit input pins, PE,, PE and PE are connected to threeinput conductors l, 5, 6 by three wires 21, 22 and 23: a main circuitoutput pin PU is connected to output conductor 7 by the wire 24; aground pin PM is connected to the ground conductor 9 by wire 25, and amain circuit feed pin PA is connected to the feed conductor 8 by thewire 26.

The logic elements of the auxiliary fault-detecting circuit comprise alogic unit 20, having three inputs 13;14, 15 and an output 16, a feedconductor 31 and a ground conductor 32. The three input conductors l3,l4 and i5'are respectively connected to the three main circuit inputconductors l, 5, 6. The logic unit is designed, so as to produce at itsoutput 16 the same logic value which should be present at the output 7of the main circuit, when the same logic values present at the inputconductors of the main circuit, 4, 5, 6 are also present at the inputsof the logic unit 20, and the operation of the main circuit is correct.The auxiliary circuit furthermore comprises a diversity unit having twoinputs EA and EB connected respectively to the output 16 of the logicunit 20 and to the output 7 of the main circuit and a flip-flop 17. Theoutput UC of the diversity unit is connected to input ES of flip-flop17, whose outputs UD and UN are connected, through the wires 33 and 34,to the pins AD and AN. The auxiliary circuit is fed, by an appropriatesource of voltage, through an auxiliary feed pin AA and the wire 35connecting it to the conductor 36 feeding the flip-flop 17 and conductor31 feeding the logic unit 20. The flip-flop 17 is connected by groundconductors 37 and 32 to the main circuit ground conductor 9. Theresetting input ER is connected to the feed conductor 36 by adifferentiating device such as capacitor 38. By this means, every timethe feeding voltage is restored to the auxiliary circuit after aninterruption, the flip-flop is automatically reset into the DOWNcondition by a short pulse transmitted through the capacitor 38 or thedifferentiating device in place thereof. Not all logic elements of theauxiliary fault-detecting circuit need actually be present as some ofthem may be combined to simplify the circuit. The operation is asfollows: 7

It is assumed that feeding of the auxiliary unit is on. During normaloperation the logic values applied to the inputs of the main circuit arealso applied to the inputs of the auxiliary logic unit, and thereforethe logic values at output 7 of the main unit and at output 16 of theauxiliary unit are equal, except during the transients due to thedifference in operating speed of the main circuit and the auxiliaryunit. Therefore the output UC of the diversity unit 30 will be, for thegreater part of the time,

at ZERO level, save for short pulses of level ONE, due to the timedifferences. The flip-flop E7 is so designed, as to be relatively slowin passing from the DOWN to'the UP position, thus being insensitive tothese short level ONE pulses, and thus remains in the DOWN condition. Incase of failure of'the main circuit, its output value is different fromthe output of the auxiliary logic unit, the diversity unit output goesto value ONE for a time sufficient to set the flip-flop 17 in the UPcondition.

' A signal ONE then appears on its direct output UD and consequently onpin AD, thus signalling to the external circuit the presence of a faultin the unit.

A different mode of operation may also be used, whereby thefault-detecting circuit normallyis not being fed, and therefore nosignal ONE is present on outputs AN or AD. The feeding voltage isapplied only when the correct operation of the apparatus is beingchecked, and this may happen at regularly spaced intervals of time, asduring routine maintenance operations, or in connection with theexecution of particular test programs which are able to put all thecircuit elements of the apparatus in all possible conditions, thusdetecting the existence of faults which may affect the operation only invery exceptional cases, and therefore may not be detected in the normaloperation, if the first described mode of operation is used.

The indicated disposition is able not only to detect faults in maincircuit 3, but also faults affecting some connections between the maincircuit and the external pins, for example, the wire 26 connecting thefeed pin PA to the feed conductor 8. The failure of the feeding voltageof the main circuit necessarily causes the malfunctioning of the same,and therefore is signalled. The same disposition also allows detectionof the eventual defective operation of the auxiliary logic unit 20,except in the very improbable case where a fault appears on the maincircuit at the same time, also causing its defective operation. In caseof a break in wire 25, the failure of the common ground connection willcause the fault operation of flip-flop 17, which is convenientlydesigned, so that the failure of the ground connection will bring thewhole circuit up to the feeding voltage, therefore causing level ONEsignals to appear on both outputs AN and AD, If the external circuit isprovided with a circuit able to detect the contemporary presence of ONElevels on both outputs, such a condition will be signalled as a fault.

In normal operation the faultdetecting circuit cannot detect a fault ofthe same circuit which would be able; to maintain a steady ZERO level onoutput UD and a steady ONE level on output UN of the flip-flop 17. Sucha fault may be detected by periodically checking the operation of thefault-detecting device, for example, interrupting the feeding of themain circuit, and ascertaining that in such condition the auxiliarycircuit gives a fault signal.

The fault-detecting circuit as described is unable to detect faults dueto the interruption of only one ofwire 21, 22, 23. As such interruptionsare relatively common, it is convenient to provide means for theirdetection.

If one of the input wires, for example, wire 21 is interrupted, theassociated input conductor 4 assumes a voltage which is determined bythe voltages of the remaining input conductors S and 6 and by thestructure and characteristics of the main circuit 3. In general thevoltage assumed by the conductor 4 in such condition will be differentfrom both V and V and in particular, may be limited betweenpredetermined voltage values VS and V8,, whereby For a given structureof circuit 3, and given signal combinations on conductors 5 and 6, whichdoes not happen in and of itself, it is generally possible to predisposea proper circuit, formed, for example, by a voltage divider fed from thefeeding voltage of the auxiliary circuit, and using suitable resistanceof proper value, so that, for one of the most frequent signalcombinations on conductors 5 and 6 the voltage of the conductor dremains in the above indicated limits. FIG. ill shows a circuitarrangement of this type. The auxiliary circuit comprises swam a doublethreshold unit 40 and three voltage dividers formed by resistors 1 and 46, whose central points 37, 48, 49 are respectively connected to inputconductors 4, g and 6 of the main unit, and to input terminals of thedouble threshold unit 40, whose output is connected by conductor 50 to asetting input of flip-flop 17.

The feeding of the double threshold unit 10 and of the voltage dividersis provided through conductor 51 and the auxiliary feeding pin AA, andthe ground connection is assured by connection to the common groundconductor 9 and ground pin PM.

By means of this arrangement, if for example wire 21 is interrupted, itis generally possible, by choosing the proper values of the resistorsforming the voltage divider, to provide that conductor 4 assumes avoltage within a range between VS and V8,, which, applied to an input ofthe double threshold unit, causes a signal ONE to be applied to asetting input of flip-flop 17, which goes into the UP condition andsignals a fault to the exterior circuit. The threshold unit has a veryhigh input impedance so that the resistors forming the voltage dividermay have resistances sufficiently high, as not to sensibly affect theoperation of the main circuit.

The fault detector cannot in general detect a break in wire 24connecting the output conductor 7 of circuit 3 to the output pin PU.This fault can, however, be detected by the auxiliary circuit of anintegrated unit logically following the faulty integrated unit. In fact,a break in the output wire of an integrated unit is equivalent to theinterruption of an input wire of the units having one input'connected tothe said output wire. FIG. 12 represents an example of a succession ofinterconnected integrated units. Unit 101 has its output connected to aninput of each one of the integrated units 103 and 104; units 102, 1.03,104 and 105 have their outputs connected to inputs of units 106, 107 and103 as shown. An interruption of the output wire of unit 101 is detectedas an interruption of an input wire in units 103 and 104, which will beindicated as defective. The examination of the connection network willestablish that the failure is very probably due to an interruption inthe output wire of unit 101, as it is highly improbable that both units103 and 104 are subject to the simultaneous interruption of their inputwires.

In the event of interruption of the output of unit 103, it is notpossible to establish whether the fault is in the output of unit 103 orthe input of unit 106, and one of such units will be substituted, and acheck made to determine if such substitution causes the disappearance ofthe fault. In case of a failure signalled on unit 107, it may be dueeither to a fault in the unit, or to an interruption of the outputwires'of units 102, 104 or 107.

The examination of the interconnection network will limit the number ofunits which may be involved as for example if unit 108 is operatingcorrectly, only units 102, 104 and 107 may be affected by a fault.

In any case it is seen that the number of possibly defective units, incase a fault is signalled on a given unit, is limited to the same unitand to a restricted number of units immediately preceding the same, thatis, those units whose outputs are connected to an input of the givenunit.

As shown hereinbefore, the technique to be used for fabricating theauxiliary fault-detecting circuitry must be com patible with thetechnique employed for fabricating, on the same chip, the main circuit,but may be substantially different, in the light of the peculiarrequirements and characteristics of the auxiliary circuit, theserequirements being, as shown, reduced dimension, reduced energyconsumption, outstanding reliability, whereas the speed requirements arelow.

Therefore, the integrated circuit technique known as Metal-Oxide-Semiconductor, (MOS) using as basic element the Field-EffectTransistor (FET) appears to be remarkably suitable for the fabricationof the auxiliary circuit. The MOS technique and the FET elements arewell known in the art, and are described for example in the bookIntegrated Circuits, Design Principles and Fabrication," by Raymond M.

Warner .lr., published by McGraw-I-Iill New York, 1965. The possibilityof obtaining any logical circuit combination, through the use of FieldEffect Transistor, is shown in the article Integrated circuits savespaceand time" by D. E. Farina and D. Trotter, published by the magazineElectronics," Oct. 4, 1965. As is shown in these publications, thecircuit fabricated according to this technique is characterized by smallenergy requirement, high input impedance, high reliability, lower speedof operation.

Some examples of fault-detecting circuits in a typical case are nowdescribed. The main circuit is a NAND gate, having three inputs,designed according to Diode-Transistor Logic. In FIG. 13 the maincircuit is identified by thick lines. It comprises a transistor 61, ofthe NPN-type and three input diodes 52, 53, 54. The anodes of the diodesare connected to a point 55 to which the base of transistor 61 is alsoconnected through two series connected diodes 62 and 63.

Point 55 is also connected to the feed pin PA through a resistor 57 ofrelatively high resistance. The collector of transistor an is connectedto the feed pin PA through a resistor 56 of relatively low resistance.Two resistors 50 and 59 connect the base and the emitter of transistor61 respectively to the ground pin. v

The well-known method of operation of the circuit is briefly continued.If at least one of the inputs PE PE ,-PE is at logic value ZERO, that isthe voltage V =0 Volt, point 55, and, therefore, the base of transistor61 are also at 0 Volt, the transistor is off, the output 60, connectedto its collector, goes toa voltage near to V (for example 5 Volt) thatis to the logic value ONE. If all inputs are at logic value ONE, thatis, at a voltage close to 5 Volt, point 55 reaches a voltage sufficientto render transistor 61 conductive, and the output then goes to 0 Volt,that is to logic value ZERO.

This may be expressed, according to the B oolean logic and symbology, bythe expression u qTEF d-l-E-I-c in which u is the logic value of output,and a, b, c are the logic values of the inputs.

Different methods may be chosen to design the faultchecking circuit,according to the degree of reliability which is desired. As thetransistor 61 is the circuit element most subject to failures, thesimplest solution represented in FIG. 13 may be adopted, wherein thefunction of the auxiliary circuit is merely that of supervising theoperation of the transistor.

As the transistor circuit embodies the logic function of inversion, thelogic value at point 55, in the case of correct operation, is thenegated one of the value at the output 60. If both these values areequal, the operation of the transistor is defective. Therefore, asindicated in FIG. 13, the logic auxiliary unit 20 and the diversity unit30 of FIG. 10 may be replaced by a simple identity unit 64, having aninput connected to point 55, and the other connected to output 60. Thisidentity unit produces a signal ONE on its output if both inputs havethe same value, thus causing the flip-flop 17 to go into the UPcondition and to signal the fault.

If the auxiliary circuit is also required to supervise the operation ofthe input circuit formed by the diodes 52, 53, 54, the identity unit ispreceded by an AND gate 65 having three inputs each connected to one ofthe input conductors 71, 72, 73 of the main circuit, as shown by FIG.14. If the main circuit is operating correctly, and a, b, c, are thelogic fies at inputs '71, 72, 73, the output 60 is at the logic valuea.b.c.,this value is the negated one of the value a.b.c. at the outputof the AND gate 65, and the output of the identity circuit 64 is ZERO.In the event of defective operation of the main circuit there isidentity of values at both inputs of the identity circuit, andconsequently a signal of level ONE at its output, which causes theflip-flop 17 to go into the UP condition and to signal the fault.

If, moreover, the integrity of the input wires 21, 22, 23 must besupervised, the three input conductors 71, 72, 73 are connected to thethree inputs of a double threshold unit 67. Assuming that the wire 21 isbroken, and that at least one of inputs P13 and PB is at 0 Volt, point55 is also at 0 Volt, even if assume input PE, is at voltage V (v); Thiscondition is not signalled as a fault, as the same happens if wire 21 isnot broken, as in a NAND gate, the output does not depend upon singleinput values, as long as at least one input is ZERO.

if, on the contrary, both inputs PE and Mi are at voltage V,, and thewire Zll is broken, the voltage at point 55 is determined by the voltagedrop across the diodes 62 and 63 and across the base-emitter junction oftransistor 61. This voltage valve is intermediate value V0 and value 1,.Conductor 21 will assume a fioating" value not substantially lower thanthe voltage at point 55. By properly choosing the characteristics ofcomponents and adjusting the threshold values V8 and VS, of thethreshold circuit 67 it is possible to have conductor 71 assume avoltage ranging between V8,, and V8,, thus causing the double thresholdunit to provide, at its output, a signal ONE which sets the flip-flop 17at its UlP position and generates a fault signal.

For main circuits different from the one indicated in the example, theinterruption of an input wire may not be adequate for permitting thevoltage of the associate input conductor to assume a value rangingbetween the threshold values, thus revealing the fault. It may thereforebe necessary, as previously shown, to provide suitable circuitarrangements to obtain the desired effect through the heretoforementioned volt age divider.

The voltage divider is only one example of a circuit which may beeffective for obtaining the desired effect. The circuit arrangements tobe used are different according to the structure of the main circuit,and it may include not only passive elements such as resistors, but alsononlinear components such as diodes, or active elements as transistors.it is known that all these elements may be easily obtained by MOStechnique. It is therefore obvious that in most cases it will bepossible to design a circuit arrangement capable of detecting thefloating condition of an input conductor, due to the interruption of anassociated wire, and apply to the conductor a voltage suitable forpermitting the double-threshold unit to render a ONE signal at itsoutput for a particular combination of input signals.

What i claim is:

1. An integrated circuit assembly comprising: a main circuit assemblyand a fault-detecting circuit assembly on a unitary substrate, Said maincircuit assembly including a plurality of check points and input andoutput circuits and providing output binary values responsive to inputsignals appearing at said input circuits, said binary values beingrepresented by a first voltage level for one state and a second voltagelevel of different magnitude for the other state; said fault-detectingcircuit assembly including logic means for obtaining a binary checkvalue responsive to signals appearing at said check points, meansinterconnecting said fault-detecting circuit assembly to predeterminedones of said check points, comparing means for comparing the binarycheck values against the output binary values of said main circuit; saidfault-detecting circuit assembly further including threshold detectingmeans having inputs connected to predetermined checlt points of saidmain circuit awembly, said threshold detecting means being responsive tosaid inputs to render an output of predetermined binary value when oneor more of said inputs of said threshold detecting means assumes avoltage intermediate said first and second voltage levels, memory meansfor storing the results of the comparison effected by said comparingmeans, means for communicating the output binary value of said thresholddetecting means to said memory means, said memory retaining theinformation received from said threshold detecting means for apredetermined period of time, and means for signaling the contents ofsaid memory means external to said integrated circuit assembly.

2. An integrated circuit assembly comprising a main circuit and anauxiliary fault-detecting circuit, both of said circuits being disposedon a unitary chip, said main circuit being connected to receive aplurality of binary input signals and responsive thereto to generate abinary output signal representing the binary result of a predeterminedlogical operation performed on said binary input signals by said maincircuit, said fault-detecting circuit comprising circuit elements havinga slower speed of response than the circuit elements of said maincircuit, said fault-detecting circuit being connected to receive aplurality of binary signals present in said main circuit and responsiveto the binary signals received thereby to generate an output faultsignal at an output point thereof when said binary signals receivedthereby fail to satisfy a predetermined criterion for the properoperation of said main circuit, memory means disposed on said chipcoupled to said output point and responsive to the occurrence of saidfault signal for storing a fault indicium and for delivering an outputsignal representing'said stored fault indiciurn, said memory means beingprovided with a reset terminal coupled to receive a stimulus generatedexternal to said chip for clearing said fault indicium from said memorymeans, said memory means maintaining each fault indicium stored therebyuntil said stimulus is received, an output lead for said chip, and meansfor coupling said output lead to said memory 3. The integrated circuitassembly of claim 2, wherein said binary signals comprise afirst'voltage level for representing one binary value and a secondvoltage level for representing the other binary value, wherein saidfault-detecting circuit further comprises a threshold detecting meansconnected to receive predetermined binary signals present in said maincircuit, said threshold detecting means being responsive to the binarysignals received thereby to generate an output signal when at least oneof said binary signals received thereby assumes a voltage intermediatesaid first and second voltage levels, and wherein means is provided forcoupling said memory means to said threshold detecting means for storingin said memory means a fault indicium when said threshold detectingmeans output signal is generated.

4. The integrated circuit assembly of claim 2, wherein saidfault-detecting circuit comprises a logic unit and comparing means, saidlogic unit being connected to receive said binary input signals receivedby the main circuit and responsive to the binary signals receivedthereby to generate a binary check signal corresponding to the binaryoutput signal generated by said main circuit when said main circuit isproperly operative, said comparing means being coupled to receive saidbinary check signal and the binary output signal generated by said maincircuit, said comparing means delivering said output fault signal whensaid binary output signal received thereby fails to correspond to saidbinary check signal.

5. The integrated circuit assembly of claim 4, wherein said binarysignals comprise a first voltage level for representing one binary valueand a second voltage level for representing the other binary value,wherein said fault-detecting circuit further comprises a thresholddetecting means connected to receive predetermined binary signalspresent in said main circuit, said threshold detecting means beingresponsive to the binary signals received thereby to generate an outputsignal when at least one of said binary signals received thereby assumesa voltage intermediate said first and second voltage levels, and whereinmeans is provided for coupling said memory means to said thresholddetecting means for storing in said memory means a fault indiciurn whensaid threshold detecting means output signal is generated.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Pat t N 3 DatedJune 29 1971 l Georges Kassabgi It is certified that error appears inthe above-identified patent and that said Letters Patent are herebycorrected as shown below:

Column 8, line 26, after "memory" insert means for providing said memorymeans output signal on said output lead.

Signed and sealed this 18th day of April 1972.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. ROBERT GOTTSCHALK Attesting Officer Commissionerof Patents USCOMM-DC 50375-P69 FORM PO-105O (10-69) 0 u s, covsnumsnvPRINTING OI'FICE was 0-366-33A

1. An integrated circuit assembly comprising: a main circuit assemblyand a fault-detecting circuit assembly on a unitary substrate, said maincircuit assembly including a plurality of check points and input andoutput circuits and providing output binary values responsive to inputsignals appearing at said input circuits, said binary values beingrepresented by a first voltage level for one state and a second voltagelevel of different magnitude for the other state; said fault-detectingcircuit assembly including logic means for obtaining a binary checkvalue responsive to signals appearing at said check points, meansinterconnecting said fault-detecting circuit assembly to predeterminedones of said check points, comparing means for comparing the binarycheck values against the output binary values of said main circuit; saidfault-detecting circuit assembly further including threshold detectingmeans having inputs connected to predetermined check points of said maincircuit assembly, said threshold detecting means being responsive tosaid inputs to render an output of predetermined binary value when oneor more of said inputs of said threshold detecting means assumes avoltage intermediate said first and second voltage levels, memory meansfor storing the results of the comparison effected by said comparingmeans, means for communicating the output binary value of said thresholddetecting means to said memory means, said memory retaining theinformation received from said threshold detecting means for apredetermined period of time, and means for signaling the contents ofsaid memory means external to said integrated circuit assembly.
 2. Anintegrated circuit assembly comprising a main circuit and an auxiliaryfault-detecting circuit, both of said circuits being disposed on aunitary chip, said main circuit being connected to receive a pluralityof binary input signals and responsive thereto to generate a binaryoutput signal representing the binary result of a predetermined logicaloperation performed on said binary input signals by said main circuit,said fault-detecting circuit comprising circuit elements having a slowerspeed of response than the circuit elements of said main circuit, saidfault-detecting circuit being connected to receive a plurality of binarysignals present in said main circuit and responsive to the binarysignals received thereby to generate an output fault signal at an outputpoint thereof when said binary signals received thereby fail to satisfya predetermined criterion for the proper operation of said main circuit,memory means disposed on said chip coupled to said outPut point andresponsive to the occurrence of said fault signal for storing a faultindicium and for delivering an output signal representing said storedfault indicium, said memory means being provided with a reset terminalcoupled to receive a stimulus generated external to said chip forclearing said fault indicium from said memory means, said memory meansmaintaining each fault indicium stored thereby until said stimulus isreceived, an output lead for said chip, and means for coupling saidoutput lead to said memory
 3. The integrated circuit assembly of claim2, wherein said binary signals comprise a first voltage level forrepresenting one binary value and a second voltage level forrepresenting the other binary value, wherein said fault-detectingcircuit further comprises a threshold detecting means connected toreceive predetermined binary signals present in said main circuit, saidthreshold detecting means being responsive to the binary signalsreceived thereby to generate an output signal when at least one of saidbinary signals received thereby assumes a voltage intermediate saidfirst and second voltage levels, and wherein means is provided forcoupling said memory means to said threshold detecting means for storingin said memory means a fault indicium when said threshold detectingmeans output signal is generated.
 4. The integrated circuit assembly ofclaim 2, wherein said fault-detecting circuit comprises a logic unit andcomparing means, said logic unit being connected to receive said binaryinput signals received by the main circuit and responsive to the binarysignals received thereby to generate a binary check signal correspondingto the binary output signal generated by said main circuit when saidmain circuit is properly operative, said comparing means being coupledto receive said binary check signal and the binary output signalgenerated by said main circuit, said comparing means delivering saidoutput fault signal when said binary output signal received therebyfails to correspond to said binary check signal.
 5. The integratedcircuit assembly of claim 4, wherein said binary signals comprise afirst voltage level for representing one binary value and a secondvoltage level for representing the other binary value, wherein saidfault-detecting circuit further comprises a threshold detecting meansconnected to receive predetermined binary signals present in said maincircuit, said threshold detecting means being responsive to the binarysignals received thereby to generate an output signal when at least oneof said binary signals received thereby assumes a voltage intermediatesaid first and second voltage levels, and wherein means is provided forcoupling said memory means to said threshold detecting means for storingin said memory means a fault indicium when said threshold detectingmeans output signal is generated.